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> No.1524[元記事へ]
The real plate load line is not straight, because of screen grid current.
On virtual Ep-Ip* plane (Ip* = Ip + b * Ig2, red dashed line),
the virtural load line would be straight.
Your load line by throughline corresponds to dasshed line
and your points are for real plate current,
so the load line and points are not coincident.
Here is the code to draw virtual and real load lines.
p <- tKT66T
Ep <- seq(0, 700, by=2) # plate voltage
Eg <- seq(0, -70, by=-5) # control grid voltage
Ebb <- 360 # supply voltage
b <- 0.5 # screen tap ratio
ip <- touter(function(p, ep, eg) {
eg2 <- Ebb + (ep - Ebb) * b
Ipp(p, ep, eg, eg2)
}, p, Ep, Eg) # plate current (matrix of Ep x Eg)
ig2 <- touter(function(p, ep, eg) {
eg2 <- Ebb + (ep - Ebb) * b
Ig2(p, ep, eg, eg2)
}, p, Ep, Eg) # screen grid current (matrix of Ep x Eg)
g.plate(ip, 700, 3000, Ipmax=0.2)
matlines(Ep, ip + ig2 * b, lty=2, col="red")
Eg0 <- -25
RL <- 3.5e3
ei <- c(-Eg0, 0, Eg0)
z <- trans.se(p, ei, Ebb, Eg0, RL, rUL=b) # in UL, you don't have to specify Eg2, Eg2 <- Ebb
# virtual load line which corresponds dashed red line
vip <- z$ip + z$ig2 * b # virtual plate current
throughline(z$ep[2], vip[2], -1/RL, col="blue")
points(z$ep, vip, col="blue", pch=19)
# real plate load line which corresponds solid red line
points(z$ep, z$ip, col="darkgreen", pch=19)
ei <- seq(-Eg0, Eg0, len=101)
z <- trans.se(p, ei, Ebb, Eg0, RL, rUL=b)
lines(z$ep, z$ip, col="darkgreen")
In designing the circuit, you should use virtual Ep-Ip* and the virtual load line
and the power output is determined by this virtual load line.
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